Progress! Got the display to work on 6.12.6.
Took a lot of debugging and reading out the registers on the display bridge. The PLL was locking, and I could get the bridge to show a colorbar pattern on the screen by writing to the 0x3C register. Issue seemed to be between the iMX and the bridge, on the DSI link. I read out the error registers, and on 0xF6 I saw 0x40, or LOSS_OF_DP_SYNC_LOCK_ERR. 0xF0 was clean of errors, which means that PHY was clean. 0xF1 only set CHA_DSI_PROTOCOL_ERR, which makes sense if it lost sync. The packets are good, the link is good, but it’s losing sync. Seemed like a clocking issue.
Bisecting the changes between these releases showed me this change to how the pixel clock is generated. This was made upstream.
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
- hws[IMX8MP_CLK_MEDIA_DISP1_PIX] = imx8m_clk_hw_composite_bus_flags("media_disp1_pix", imx8mp_media_disp_pix_sels, ccm_base + 0xbe00,CLK_SET_RATE_PARENT);
+ hws[IMX8MP_CLK_MEDIA_DISP1_PIX] = imx8m_clk_hw_composite("media_disp1_pix", imx8mp_media_disp_pix_sels, ccm_base + 0xbe00);
Reverting that, rebuilding (and applying all the MNT patches) brought the display back.
This change seems to make the pixel clock go from 148.5MHz to 162MHz. Maybe this is too fast for the DSI link to handle?
stock 6.12.6 and 7.1.7:
video_pll1 162000000
video_pll1_out 162000000
media_disp1_pix 162000000
media_disp1_pix_root_clk 162000000 32e80000.display-controller pix
6.8.12, and the patched build:
video_pll1 1039500000
video_pll1_out 1039500000
media_disp1_pix 148500000
media_disp1_pix_root_clk 148500000 32e80000.display-controller pix