Just curious if there are any updates on this. Has the design been finalized?
Coincidentally, I’ve been (and still working on) finalizing revision 2 this week. I posted some routing shots on my Twitter, too.
So many questions:
- What tooling do you use to program the FPGA?
- Do you use another Reform and JTAG?
- Which JTAG interface?
- Presumably this module will also work with the Pocket Reform
I can’t wait for this, so many possibilities (mess around with stack machines (M17, rtx 2000, etc), maybe Lisp Machine inspired stuff, and of course more prosaic stuff like RISC-V)
- Currently, the default P&R tool is Vivado. The free webpack edition can target the XC7K160T, but for the bigger XC7K325T you need a Vivado license. The FPGAs are pin compatible.
- I am building the default SoC with LiteX (and
linux-on-litex-vexriscv), this way you don’t have to touch the Vivado tooling/GUI. LiteX will automatically run the P&R tooling as part of the (commandline based) build process.
- Theoretically you can now make a bitstream with the reverse engineering effort prjxray instead of Vivado, but I haven’t tried it yet. This would be de desirable of course.
- For flashing / JTAG I am using a cheap clone of the Xilinx Platform Cable USB, which is supported by
- The module will also work with the Pocket Reform motherboard, yes.
I managed to bring up a full Linux system on a dual core RISC-V soft CPU (VexRiscV) and the LiteX SoC, and integreate the module in MNT Reform. Photos:
I have some questions related to FPGA module sold through
I don’t have any experience with creating logical circuits, nor with FPGA. Therefore:
How useful would be such a module for “normal user”? Can this be used to just load some CPU created by someone else (e.g. RISC-V), and just try it?
Above page mentions “Please note that building gateware for XC7K325T requires Vivado Enterprise license.”. According to official data, XC7K325T is bigger (it has 326k cells, while XC7K160T has 162k cells). Is this software required to “program” chip with CPU, or to prepare (compile) logical cells? My mental model of workflow is:
a) preparation of description of chip, i.e. connections of all logical gates (or on whatever abstraction level FPGA works); this is a bit like writing source code
b) compilation of above description to binary format understood by particular FPGA; this is similar to compiling source code to binary for amd64 or arm64
c) binary is programmed on FPGA,
Is my description correct, and which steps require software available in Debian versus proprietary/commercial software?
- Will you sell “empty shells” of MNT Reform (of Pocket Reform) without CPU module? It is not possible to build it from what is available in shop (e.g. mainboard is missing). We have now older ARM, soon new, faster ARM, later FPGA… Experimentation and playing will require disassembling laptop, which makes treating MNT Reform as daily driver more difficult (or discourages experimentation/trying different modules).
Sorry if my questions are naive; I’m trying to understand topic and decide whether buying FPGA for MNT Reform makes sense.
- Yes, this will become more useful to non-FPGA-developers as soon as someone publishes complete cores for it.
- Your mental model is correct. To just load the FPGA bitfile into the FPGA, Vivado is not required. This can currently be done with a JTAG cable and
xc3sprog. But in the future, optimally there would be a bootloader stored in the SPI flash that would then load the real bitfile off SD card via a menu system, for example. This has not been developed for our module yet, though.
- Not yet. Without the default module it will probably only be around 100 EUR cheaper though.