U-Boot and internal screen?

MNT Reform
10

I got colour bars. :slight_smile: The stripes patterns don’t work, but the other patterns do.

# Set DSI clock to 486 MHz
=> i2c mw 0x2c 0x0a 0x06
# Single Channel, 4 DSI lanes
=> i2c mw 0x2c 0x10 0x26
# Enhanced framing and ASSR
=> i2c mw 0x2c 0x5a 0x05
# 2 DP lanes w/o SSC
=> i2c mw 0x2c 0x93 0x20
# 2.7 Gbps DP data rate
=> i2c mw 0x2c 0x94 0x80
# Enable PLL and confirm PLL is locked
=> i2c mw 0x2c 0x0d 0x01
=> i2c md 0x2c 0x0a 1
000a: 87    .

# Enable ASSR on display
=> i2c mw 0x2c 0x64 0x01
=> i2c mw 0x2c 0x75 0x01
=> i2c mw 0x2c 0x76 0x0a
=> i2c mw 0x2c 0x77 0x01
=> i2c mw 0x2c 0x78 0x81
# Train link and confirm link is trained
=> i2c mw 0x2c 0x96 0x0a
=> i2c md 0x2c 0x96
0096: 01    .

The following timing values are likely wrong, I need to correct them using the calculations in section 9.2.1.2.2 in the data sheet and the EDID values above.

# Line length 1920
=> i2c mw 0x2c 0x20 0x80
=> i2c mw 0x2c 0x21 0x07
# Vertical display size 1080
=> i2c mw 0x2c 0x24 0x38
=> i2c mw 0x2c 0x25 0x04
# HSync pulse width 40
=> i2c mw 0x2c 0x2c 0x28
# VSync pulse width 4
=> i2c mw 0x2c 0x30 0x04
# Horizonal back porch 40
=> i2c mw 0x2c 0x35 0x28
# Vertical back porch 4
=> i2c mw 0x2c 0x36 0x04
# Horizonal front porch 40
=> i2c mw 0x2c 0x38 0x28
# Vertical front porch 4
=> i2c mw 0x2c 0x3a 0x04

# Enable color bar
=> i2c mw 0x2c 0x3c 0x10
# Enable video stream, ASSR, enhanced framing
=> i2c mw 0x2c 0x5a 0x0d

Section 9.2.1.2.5 Example Script in the data sheet was extremely helpful in getting to this milestone, the above is an adaption of it. (After my own attempts didn’t get me a picture…)

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